module np_jtag_top(
// Clocks and resets
// input  wire         cfg_ext_clk,
// input  wire         cfg_ext_clk_rst,
input  wire         cfg_clk,
input  wire         cfg_rst,

// JTAG interface    
input  wire         jtag_trst,
input  wire         jtag_tms,
input  wire         jtag_tdi,
output wire         jtag_tdo,
output wire         jtag_tdo_en,
// input  wire         jtag_tck,
input  wire         jtag_clk,   //from np_32ME_jtag_top
input  wire         jtag_clk_n, //from np_32ME_jtag_top

// Scan Signals
input  wire         scan_mode,
input  wire         scan_set_rst,

output wire [31:0]  cfg_addr_o         ,
output wire [31:0]  cfg_wr_data_o      ,
output wire         cfg_wr_en_o        ,
output wire         cfg_rd_en_o        ,
input  wire [31:0]  cfg_rd_data_i      ,
output wire         jtag_occupy
);

// -------------------------
// Registers and nets
// -------------------------    

wire  jtag_rst    ;
wire  jtag_ser_in ;
wire  jtag_capture;
wire  jtag_shift  ;
wire  jtag_update ;

wire  jtag_cfg_sel;
wire  jtag_cfg_tdo;

// External CFG control bus
wire [31:0]   cfg_ext_addr      ;
wire [31:0]   cfg_ext_wr_data   ;
wire          cfg_ext_wr_en     ;
wire          cfg_ext_rd_en     ;
wire [31:0]   cfg_ext_rd_data   ;
wire          cfg_ext_ack       ;
// CFG control bus 
wire [31:0]   cfg_addr          ;
wire [31:0]   cfg_wr_data       ;
wire          cfg_wr_en         ;
wire          cfg_rd_en         ;
wire          cfg_ack           ;
wire [31:0]   cfg_rd_data       ;
//scan
//wire         scan_mode          ;
//wire         scan_set_rst       ;
//cfg_ext_clk
wire         cfg_ext_clk        ;
wire         cfg_ext_clk_rst    ;
reg          jtag_cfg_sel_d1    ;

//assign cfg_ext_clk_rst = cfg_rst ;//0625.sh
assign cfg_ext_clk = jtag_clk_n;

np_jtag_ctl jtag_ctl (
    // TAP interface
    .jtag_trst          (jtag_trst),
    //input  wire         jtag_tck,
    .jtag_tms           (jtag_tms),
    .jtag_tdi           (jtag_tdi),
    .jtag_tdo           (jtag_tdo),
    .jtag_tdo_en        (jtag_tdo_en),

    // Scan interface
    .scan_mode          (scan_mode),
    .scan_set_rst       (scan_set_rst),

    // Generic JTAG register control signals
    .jtag_clk           (jtag_clk),
    .jtag_clk_n         (jtag_clk_n),
    //output  wire         jtag_clk,
    //output  wire         jtag_clk_n,
    .jtag_rst           (jtag_rst    ),
    .jtag_ser_in        (jtag_ser_in ),
    .jtag_capture       (jtag_capture),
    .jtag_shift         (jtag_shift  ),
    .jtag_update        (jtag_update ),

    // Individual JTAG registers not contained herein
    .jtag_cfg_sel       (jtag_cfg_sel),
    .jtag_cfg_tdo       (jtag_cfg_tdo)
);

np_cfg_jtag cfg_jtag (
  // JTAG interface
  .jtag_rst              (jtag_rst),
  .jtag_clk              (jtag_clk),
  .jtag_clk_n            (jtag_clk_n),
  .jtag_capture          (jtag_capture),
  .jtag_shift            (jtag_shift),
  .jtag_update           (jtag_update),
  .jtag_ser_in           (jtag_ser_in),
  .jtag_cfg_sel          (jtag_cfg_sel),
  .jtag_cfg_tdo          (jtag_cfg_tdo),
  
  // External CFG control bus
  .cfg_jtag_addr         (cfg_ext_addr),
  .cfg_jtag_wr_en        (cfg_ext_wr_en),
  .cfg_jtag_wr_data      (cfg_ext_wr_data),
  .cfg_jtag_rd_en        (cfg_ext_rd_en),
  .cfg_jtag_rd_data      (cfg_ext_rd_data),
  .cfg_jtag_ack          (cfg_ext_ack)
); 

// -----------------------------------------------------------------
// Control interface 
// -----------------------------------------------------------------
np_cfg_cdc_ctl cfg_cdc_ctl (
    // CFG External Clock and reset
    .cfg_ext_clk            (cfg_ext_clk    ),
    .cfg_ext_clk_rst        (cfg_ext_clk_rst),

    // Clock and reset
    .cfg_clk                (cfg_clk),
    .cfg_rst                (cfg_rst),

    // External CFG control bus
    .cfg_ext_addr           (cfg_ext_addr   ),
    .cfg_ext_wr_data        (cfg_ext_wr_data),
    .cfg_ext_wr_en          (cfg_ext_wr_en  ),
    .cfg_ext_rd_en          (cfg_ext_rd_en  ),
    .cfg_ext_rd_data        (cfg_ext_rd_data),
    .cfg_ext_ack            (cfg_ext_ack    ),
    
    //scan
    .scan_mode              (scan_mode   ),
    .scan_set_rst           (scan_set_rst),
  
    // CFG control bus 
    .cfg_addr               (cfg_addr   ),
    .cfg_wr_data            (cfg_wr_data),
    .cfg_wr_en              (cfg_wr_en  ),
    .cfg_rd_en              (cfg_rd_en  ),
    .cfg_ack                (cfg_ack    ),
    .cfg_rd_data            (cfg_rd_data)
);

np_access_det access_det (
  // CFG Clock and Reset
  .cfg_clk          (cfg_clk),
  .cfg_rst          (cfg_rst),

  // CFG input interfaces
  .cfg_addr         (cfg_addr   ),
  .cfg_wr_data      (cfg_wr_data),
  .cfg_wr_en        (cfg_wr_en  ),
  .cfg_rd_en        (cfg_rd_en  ),
  .cfg_ack          (cfg_ack    ),
  .cfg_rd_data      (cfg_rd_data),

  // CFG output interface
  .cfg_addr_o       (cfg_addr_o   ),
  .cfg_wr_data_o    (cfg_wr_data_o),
  .cfg_wr_en_o      (cfg_wr_en_o  ),
  .cfg_rd_en_o      (cfg_rd_en_o  ),
  .cfg_rd_data_i    (cfg_rd_data_i)
);

// Generate a synchronous reset on cfg_ext_clk
np_gen_rst_sync cfg_ext_clk_rst_sync (
  .sync_rst       (cfg_ext_clk_rst),
  .clk            (cfg_ext_clk),
  .async_rst      (cfg_rst), //jtag_trst, 0719, xym, 312p5m_rst > 50m_rst
  .scan_mode_i    (scan_mode),
  .scan_set_rst_i (scan_set_rst)
);
//21.10.12
always@(posedge jtag_clk_n or posedge jtag_rst) begin
    if(jtag_rst)
        jtag_cfg_sel_d1 <= 1'b0;
    else
        jtag_cfg_sel_d1 <= jtag_cfg_sel;
end
// Generate jtag_cfg_sel on cfg_clk  21.7.17
np_gen_pipe_dly #(.RST_VAL(0), .PIPE_DLY(2))
jtag_occupy_gen (
  .q   (jtag_occupy),
  .clk (cfg_clk),
  .rst (cfg_rst),
  .d   (jtag_cfg_sel_d1)
);
endmodule
